1. Technical Field
This disclosure generally relates to the field of semiconductor devices. Specifically, the disclosure relates to three-dimensional semiconductor structures and methods of forming three-dimensional semiconductor devices.
2. Description of the Related Art
Semiconductor devices, such as semiconductor memories, are in widespread use in consumer electronics and other applications. Consumer demand for ever higher densities of semiconductor devices has motivated manufacturers to seek methods of decreasing the size of discrete devices that typically make up a semiconductor device. The discrete devices include transistors, capacitors and resistors. The discrete devices may be fabricated using various processes such as photolithography, wet and dry etching, thin film deposition, and diffusion. Unfortunately, limits on the photolithography process, such as the wavelength of the light used, cause there to be limits on the size of the discrete devices. Consequently, the photolithography process seems to place a limit on the density of semi-conductor devices that can be achieved.
One solution to this problem, three-dimensional semiconductor structures, has been proposed to increase integration density of semiconductor devices. One such example is disclosed in U.S. Pat. No. 6,022,766 to Chen, et al. (“Chen”), in which an ordinary bulk transistor is formed in a single crystal silicon substrate and a thin film transistor (TFT) is stacked over the bulk transistor. Specifically, an amorphous silicon layer is deposited over the substrate having the bulk transistor. Then, the resulting structure is heat treated to crystallize the amorphous silicon layer and thereby to form a body layer that is generally formed of a polycrystalline silicon (“polysilicon”) material.
However, large grains in the polysilicon material can act as a carrier trap, thereby degrading the electrical characteristics of the TFT. In particular, the carrier mobility of a TFT fabricated in a polysilicon substrate is smaller than that of a bulk transistor fabricated in a single crystal silicon substrate. This decrease in carrier mobility is known to be largely due to carrier trapping in the grain boundaries of the polycrystalline material, e.g., polysilicon. As a result, the electrical characteristics of the resulting TFT are not as desirable as that of the bulk transistor.
One approach to improve the electrical characteristics of TFTs fabricated in semiconductor layers is to improve the crystalline quality of the layers by, for example, minimizing the grain boundaries incorporated into a single semiconductor device. This can be accomplished by high-temperature heat treatment or annealing of the layer, but these high temperature heat treatments can lead to degradation of the lower bulk devices. For example, the source/drain regions of the lower devices may suffer from undesirable dopant diffusion during the high temperature heat treatment step, leading to inconsistent device performance.
Another approach to forming a three-dimensional semiconductor device is disclosed in U.S. Pat. No. 6,423,614 to Doyle (“Doyle”). Doyle discloses ion implantation of hydrogen atoms on a first semiconductor substrate to form a semiconductor film separated from the bulk substrate by a damaged layer created by the hydrogen implantation. Then, a first oxidation layer is formed over the first semiconductor substrate. A second oxidation layer and a metal layer are then formed over a second semiconductor substrate. The metal layer on the second semiconductor substrate is bonded with the first oxidation layer of the first semiconductor substrate. The bulk substrate of the first substrate is delaminated from the second substrate while the first oxidation layer and the semiconductor film of the first substrate remain over the metal layer of the second substrate. The semiconductor film is planarized using a chemical mechanical polishing (CMP) process. A TFT is formed using the planarized semiconductor film as a body layer. The resulting structure having the TFT is annealed at a low temperature of about 400° C. in a hydrogen atmosphere, causing the second substrate having the metal layer and the second oxidation layer to be delaminated from the first oxidation layer of the first substrate. Then, a carrier wafer is placed onto the TFT and is delaminated from the TFT. Subsequently, the first oxidation layer and any remaining portion of the metal layer are removed. Then, the TFT is bonded with a third substrate having bulk transistors.
According to Doyle, three different delamination processes and at least three bonding processes are required to form the thin film transistor over the substrate having bulk transistors, i.e., two layers of transistors. Therefore, the process of Doyle comprises many processing steps, which complicates the overall semiconductor fabrication process.
Consequently, novel methods that can improve the electrical characteristics of thin film transistors fabricated on substrates containing bulk devices by, for example, limiting exposure of the lower bulk devices to high temperatures are desired. Further, there is a need for an improved process that includes a minimum number of processing steps, thereby simplifying the overall fabrication process.